I had made F5 boards a couple of years ago but never followed up this project. Until today, when I mounted them onto heatsinks and fired them up.
Strange thing. Increasing the resistance of the pot in the positive half of the circuit does not result in any bias setting. The same procedure at the negative half enables to set the bias on both halves and now allows to trim the positive side too.
It is not possible to bring the offset down to 0 V yet. At a bias setting of 1.3A on both halves (~600mV voltage drop over the Source resistors) the voltage drop over the JFETs' Drain resistors is ~4.3V (negative side) and ~5.7V (posistive side). The offset voltage is ~-130mV.
The second channel shows the same behaviour, but the difference between the positive and the negative half is even worse (>300mV offset voltage).
The JFETs of both channels are closely matched and I cannot see any layout or stuffing errors. Need consolation and advice:confused:
Strange thing. Increasing the resistance of the pot in the positive half of the circuit does not result in any bias setting. The same procedure at the negative half enables to set the bias on both halves and now allows to trim the positive side too.
It is not possible to bring the offset down to 0 V yet. At a bias setting of 1.3A on both halves (~600mV voltage drop over the Source resistors) the voltage drop over the JFETs' Drain resistors is ~4.3V (negative side) and ~5.7V (posistive side). The offset voltage is ~-130mV.
The second channel shows the same behaviour, but the difference between the positive and the negative half is even worse (>300mV offset voltage).
The JFETs of both channels are closely matched and I cannot see any layout or stuffing errors. Need consolation and advice:confused: