bjt jfet CFP diff input stage

I im designing a new amplifier and found this interesting article:

Memory Distortion Philosophies - Part 4 : Circuits

As from the link i would like to simulate this input stage in LTSPice...and if anyone could help me how to simulate for now only input stage(Linearity, Gain, SlewRate, THD, etc...)

here is example input stage only with bjt:

https://sites.google.com/site/fabaud...ge_low_mem.jpg

As you can i add p-jfet and n-jfet to bjt. Together i get all the benefits from bjt and jfet so linearity need to be perfect.

For jfet i have choose 2SK170/2sj74 from Toshiba
For bjt i have choose 2SA970/2SC2240 from Toshiba

Between Resistors R3/R4 it must go to CCS Source, and from J1/J2 Drain it gets to Current Mirror With Two Bjt Transistors (2SA970/2SC2240).

What do you guys suggest to be the best CCS Source and Current Mirror or should i use other suggetions?

I im attaching LTSpice file with schematic if someone could add commands to simulate only this input stage and uplodad it here so we can discuss here what is better and to fine tune this input stage (High Linearity, Slew Rate...)

Many Thanks.

And if someone can add models Toshiba 2SA970/2SC2240 and JFETs (2SK170/2SJ74 Toshiba).

Attached Files

Lavardin.asc (2.8 KB)